library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testbench_coder is
end testbench_coder;

architecture Behavioral of testbench_coder is
signal tb_datain, tb_dataout, tb_key : std_logic_vector(127 downto 0);
signal tb_start, tb_clk, tb_rst, tb_finish : std_logic;

begin
	AesCoder: entity work.coder(Structural)
		port map (start => tb_start,
					 clk => tb_clk,
					 rst => tb_rst,
					 datain => tb_datain,
					 key => tb_key,
					 dataout => tb_dataout,
					 finish => tb_finish);

	-- Dane testowe z FIPS-197 / Appendix B (s. 33) !! PODAWANE WIERSZAMI !!
	tb_datain <= X"328831e0435a3137f6309807a88da234";
	tb_key <= X"2b28ab097eaef7cf15d2154f16a6883c";

process	-- Generacja zegara
begin
	tb_clk <= '0';
	wait for 5 ns;
	tb_clk <= '1';
	wait for 5 ns;
end process;

process	-- Reset + start
begin
	tb_start <= '0';

	tb_rst <= '1';
	wait for 20 ns;
	tb_rst <= '0';
	wait for 20 ns;
	tb_rst <= '1';
	wait for 20 ns;

	tb_start <= '1';
	
	wait;
end process;

end Behavioral;

